1. Field of the Invention
The present invention relates to a semiconductor memory having a power supply startup sequence and, more particularly, to a semiconductor integrated circuit device having a power supply startup sequence that enhances the capability of a negative power supply generation circuit.
2. Description of the Related Art
A semiconductor integrated circuit device and, more particularly, a semiconductor memory, must drive all internal power supplies at a predetermined voltage at power supply startup within a startup time that is defined by the specifications. Internal power supplies are driven to predetermined voltages in accordance with the charging of parasitic capacitances or stabilizing capacitances that are formed in the semiconductor substrate by using an external power supply Vdd. Internal power supplies include a variety of power supplies such as an intermediate power supply with an intermediate potential between the external power supply and ground power supply, a booster power supply that is higher than the external power supply, and a negative power supply that is below the ground power supply.
In the case of DRAM, which is one type of semiconductor memory, a memory cell is constituted by one transistor and one capacitor. A back gate bias power supply VBB constituting a negative power supply is applied to the back gate region of the cell transistor and a cell plate power supply constituting an intermediate power supply is applied to the opposing electrodes of the cell capacitor. Further, a pre-charge power supply for bitline pair and a negative-power-supply for wordline reset power supply as a wordline unselected power supply are required.
More particularly, power supplies of the memory core region where memory cells are formed, such as a cell-plate power supply VPL, a back gate bias power supply VBB, a bitline pre-charge power supply VBLEQ, and a word-line reset power supply VNN, and so forth, for example, are started up at a predetermined voltage by charging parasitic capacitances that include capacitances between impurity diffusion regions within the memory core region. Therefore, these internal power supplies are mutually connected via parasitic capacitances and the startup of each of the internal power supplies during the power supply startup must be performed according to a predetermined sequence, as described in Japanese Patent Application Laid Open No. S60-261099 (disclosed on Dec. 24, 1985), Japanese Patent Application Laid Open No. S63-311696 (disclosed on Dec. 20, 1988), and Japanese Patent Application Laid Open No. H6-215563 (disclosed on Aug. 5, 1994), for example.
FIG. 1 shows an example of a conventional power supply startup method. FIG. 1A shows a power supply startup sequence, where time is plotted on the horizontal axis and the voltage is plotted on the vertical axis. Further, FIG. 1B is an equivalence circuit diagram that shows in the relationship of the parasitic capacitances between the internal power supplies VPL, VBB, VNN, and VBLEQ with a ground power supply VSS. As shown in FIG. 1B, these internal power supplies are interconnected via parasitic capacitances C1 to C4. Therefore, in order to startup the internal power supplies at each of these potentials, these parasitic capacitances must be charged.
According to the power supply startup sequence shown in FIG. 1A, in phase 1a, after the booster power supply or similar has risen in accordance with the rise of the external power supply VDD and has stabilized at a predetermined potential, the startup sequence of the remaining internal power supplies begins. First, in phase 2a, while the back gate bias power supply VBB and word-line reset power supply VNN are clamped to the ground power supply VSS, the cell plate power supply VPL and bit-line pre-charge power supply VBLEQ are driven to a predetermined potential by using the external power supply VDD. When the cell plate power supply VPL and so forth reaches a predetermined potential, in phase 3a, the back gate bias power supply VBB and word-line reset power supply VNN are driven to a negative potential by means of a negative power supply generation circuit such as a pumping circuit. The cell plate power supply VPL and the like, which started up first, is fixed at a predetermined potential while the negative power supply drops to the predetermined negative potential. Further, when the negative power supply reaches the predetermined negative potential, the startup of all the internal power supplies is complete and, in phase 4a, these power supplies enter the standby state.
Thus, the startup at the predetermined potential is performed by stepping up or stepping down the positive internal power supplies and negative internal power supplies in different phases.